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1 isl54224 high-speed usb 2.0 (480mbps) multiplexer with overvoltage protection (ovp) and overvoltage indicator output isl54224 the intersil isl54224 is a single supply dual 2:1 multiplexer that can operate fr om a single 2.7v to 5.25v supply. it contains two spdt (single pole/double throw) switches configured as a dpdt. the part was designed for switching of usb data signals in portable battery powered products. the 6.5 switches were specifically designed to pass usb high speed/full speed data signals. they have high bandwidth and low capacitanc e to pass usb high speed data signals with minimal distortion. the isl54224 has ovp circuitry on the d-/d+ com pins that opens the usb in-line sw itches when the voltage at these pins exceeds 3.8v (typ) or goes negative by -0.5v (typ). it isolates fault voltages up to +5.25v or down to -5v from getting passed to the other-side of the switch, thereby protecting the usb transceivers. the digital logic in puts are 1.8v logic compatible when operated with a 2.7v to 3.6v supply. the isl54224 has an open drain oe/alm pin that can be driven low to open all switches and outputs a low when the ovp circuitry is activated. it can be used to facilitate proper bus disconnect and connection when switching between the usb sources. the isl54224 is available in 10 ld 1.8mmx1.4mm tqfn and 10 ld tdfn packages. it operates over a temperature range of -40 to +85c. features ? high-speed (480mbps) and full-speed (12mbps) signaling capability per usb 2.0 ? 1.8v logic compatible (2.7v to +3.6v supply) ? oe/alm pin to open all switches and indicate overvoltage fault condition ? power off protection ? d-/d+ pins overvoltage protection for +5.25v and -5v fault voltages ? -3db frequency . . . . . . . . . . . . . . . . . . 780mhz ? low on capacitance @ 240mhz . . . . . . . . . 3.3pf ? low on-resistance . . . . . . . . . . . . . . . . . . 6.5 ? single supply operation (v dd ) . . . . 2.7v to 5.25v ? available in tqfn and tdfn packages ? pb-free (rohs compliant) ? compliant with usb 2.0 short circuit and overvoltage requirements without additional external components applications* (see page 16) ? mp3 and other personal media players ? cellular/mobile phones ?pda?s ? digital cameras and camcorders ? usb switching related literature* (see page 16) ?see an1571 ?isl54224irtzeval1z evaluation board user's manual? typical application usb 2.0 hs eye pattern with switches in the signal path isl54224 usb transceiver usb connector d- d+ gnd hsd1+ hsd1- vdd oe/alm p vbus d- d+ gnd ovp 500 sel logic control 3.3v usb transceiver 100k hsd2+ hsd2- 3.3v time scale (0.2ns/div) voltage scale (0.1v/div) caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. june 7, 2010 fn6969.0
2 fn6969.0 june 7, 2010 pin configuration isl54224 (10 ld 1.8x1.4 tqfn) top view isl54224 (10 ld 3x3 tdfn) top view note: 1. switches shown for sel = logic ?1? and oe/alm = logic ?1?. 8 10 d- oe/alm d+ vdd 9 7 2 3 4 gnd hsd2- hsd2+ 5 sel logic control 1 6 hsd1+ hsd1- ovp 4m 4m sel hsd2- d+ hsd2+ hsd1+ gnd 1 2 3 4 5 10 9 8 7 6 d- hsd1- vdd oe/alm logic control ovp pd 4m 4m truth table oe/alm sel hsd1-, hsd1+ hsd2-, hsd2+ 0x off off 10 on off 11 off on logic ?0? when 0.5v, logic ?1? when 1.4v with a 2.7v to 3.6v supply. pin descriptions tqfn tdfn pin name description 1 2 hsd2- usb data port channel 2 2 3 hsd2+ usb data port channel 2 3 4 d+ usb data com port 4 5 gnd ground connection 5 6 d- usb data com port 6 7 hsd1- usb data port channel 1 7 8 hsd1+ usb data port channel 1 8 9 oe/alm switch enable/alarm (open drain connection) drive low to open all switches outputs low when otv is activated 9 10 vdd power supply 10 1 sel select logic control input - pd pd thermal pad. tie to ground or float table 1. usb - ovp possible situat ions and trip point voltage codec supply switch supply (v dd ) coms shorted to protected trip point oe/alm min max 2.7v to 3.3v 2.7v to 5.25v vbus yes 3.63v 3.95v low 2.7v to 3.3v 2.7v to 5.25v -5v yes -0.76v -0.29v low isl54224
3 fn6969.0 june 7, 2010 ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # isl54224iruz-t (notes 2, 3) t9 -40 to +85 10 ld 1.8x1.4mm tqfn (tape and reel) l10.1.8x1.4a ISL54224IRUZ-T7A (notes 2, 3) t9 -40 to +85 10 ld 1.8x1.4mm tqfn (tape and reel) l10.1.8x1.4a isl54224irtz (note 4) 4224 -40 to +85 10 ld 3x3 tdfn l10.3x3a isl54224irtz-t (notes 2, 4) 4224 -40 to +85 10 ld 3x3 tdfn (tape and reel) l10.3x3a isl54224irueval1z evaluation board 2. please refer to tb347 for details on reel specifications. 3. these intersil pb- free plastic packaged products em ploy special pb-free material sets; molding compounds/die attach materials and nipdau plat e - e4 termination finish, which is rohs compli ant and compatible with both snpb and pb-free soldering operations. intersil pb-free produc ts are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. these intersil pb- free plastic packaged products em ploy special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 terminatio n finish, which is rohs compli ant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requ irements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl54224 . for more information on msl please see techbrief tb363 . isl54224
4 fn6969.0 june 7, 2010 absolute maximum ratings thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5v vdd to dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5v dx to hsd1x, hsd2 x . . . . . . . . . . . . . . . . . . . . . . . . 8.6v input voltages hsd2x, hsd1x . . . . . . . . . . . . . . . . . . . . - 0.3v to 6.5v sel, oe/alm. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5v output voltages d+, d- . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5v to 6.5v continuous current (hsd2x, hsd1x) . . . . . . . . . . . 40ma peak current (hsd2x, hsd1x) (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . 100ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . >5.5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . >250v charged device model . . . . . . . . . . . . . . . . . . . . . . . >2kv latch-up tested per jedec; clas s ii level a . . . . . . at 85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld tqfn package (note 6, 7) . 210 165 10 ld tdfn package (notes 8, 9). . 58 22 maximum junction temperature (plastic package). . +150c maximum storage temperature range . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c vdd supply voltage range. . . . . . . . . . . . . . 2.7v to 5.25v logic control input voltage . . . . . . . . . . . . . . . 0v to 5.25v analog signal range v dd = 2.7v to 5.25v . . . . . . . . . . . . . . . . . . . 0v to 3.6v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is taken at the package top center. 8. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 9. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications - 2.7v to 5.25v supply test conditions: v dd = +3.3v, gnd = 0v, v sel h = 1.4v, v sel l = 0.5v, v oe/almh =1.4v, v oe/alml = 0.5v, (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units analog switch characteristics on-resistance, r on (high-speed) v dd = 2.7v, sel = 0.5v or 1.4v, oe/alm = 1.4v, i dx = 17ma, v hsd1x or v hsd2x = 0v to 400mv (see figure 3, note 15) 25 - 6.5 7 full - - 9 r on matching between channels, r on (high-speed) v dd = 2.7v, sel = 0.5v or 1.4v, oe/alm = 1.4v, i dx = 17ma, v v hsd1x or v hsd2x = voltage at max r on , (notes 14, 15) 25 - 0.2 0.45 full - - 0.5 r on flatness, r flat(on) (high-speed) v dd = 2.7v, sel = 0.5v or 1.4v, oe/alm = 1.4v, i dx = 17ma, v hsd1x or v hsd2x = 0v to 400mv, (notes 13, 15) 25 - 0.3 0.5 full - - 1 on-resistance, r on v dd = 3.3v, sel = 0.5v or 1.4v, oe/alm = 1.4v, i comx = 17ma, v d+ or v d- = 3.3v (see figure 4, note 15) 25 - 12 20 full - - 25 off leakage current, i hsd1x(off) v dd = 5.25v, sel = v dd and oe/alm = v dd or oe/alm = 0v, v dx =0.3v, 3.3v, v hsd1x = 3.3v, 0.3v, v hsd2x = 0.3v, 3.3v 25 -20 1 20 na full -30 - 30 na on leakage current, i hsd1x(on) v dd = 5.25v, sel = 0v, oe/alm = v dd , v dx = 0.3v, 3.3v, v hsd1x = 0.3v, 3.3v, v hsd2x = 3.3v, 0.3v 25 - 2 3 a full - - 4 a off leakage current, i hsd2x(off) v dd = 5.25v, sel = 0v and oe/alm = v dd or oe/alm = 0v, v dx = 3.3v, 0.3v, v hsd2x = 0.3v, 3.3v, v hsd1x = 3.3v, 0.3v 25 -20 1 20 na full -30 - 30 na on leakage current, i hsd2x(on) v dd = 5.25v, sel = v dd , oe/alm = v dd , v dx = 0.3v, 3.3v, v hsd2x = 0.3v, 3.3v, v hsd1x = 3.3v, 0.3v 25 - 2 3 a full - - 4 a isl54224
5 fn6969.0 june 7, 2010 power off leakage current, i d+ , i d- v dd = 0v, v d+ = 5.25v, v d- = 5.25v, sel = oe/alm = v dd 25 - 5 13 a power off logic current, i sel , i oe/alm v dd = 0v, sel = oe/alm = 5.25v 25 - 19 26 a power off d+/d- current, i hsdx+ , i hsdx- v dd = 0v, sel = oe/alm = v dd , v hsdx+ =v hsdx- = 5.25v 25 - 0.05 1 a overvoltage protection detection positive fault-protection trip threshold, v pfp v dd = 2.7v to 5.25v, sel = 0v or v dd , oe/alm = v dd , see table 1 on page 2 25 3.63 3.8 3.95 v negative fault-protection trip threshold, v nfp v dd = 2.7v to 5.25v, sel = 0v or v dd , oe/alm = v dd , see table 1 on page 2 25 -0.76 -0.5 -0.29 v off persistence time fault protection response time negative ovp response: v dd = 2.7v, sel = 0v or v dd , oe/alm = v dd , v dx = 0v to -5v, r l = 15k 25 - 1 - s positive ovp response: v dd = 2.7v, sel = 0v or v dd , oe/alm = v dd , v dx = 0v to 5.25v, r l = 15k 25 - 2 - s on persistence time fault protection recovery time v dd = 2.7v, sel = 0v or v dd , oe/alm = v dd , v dx = 0v to 5.25v or 0v to -5v, r l = 15k 25 - 40 - s dynamic characteristics turn- on t im e, t on v dd = 3.3v, vinput = 3v, r l = 50 , c l = 50pf (see figure 1) 25 - 110 - ns turn-off time, t off v dd = 3.3v, vinput = 3v, r l = 50 , c l = 50pf (see figure 1) 25 - 70 - ns break-before-make time delay, t d v dd = 3.3v, r l = 50 , c l = 50pf (see figure 2) 25 -40-ns turn-on enable time, t enable v dd = 3.3v, v input = 3v, r l = 15k , c l = 50pf, time out of all-off state 25 - 90 - ns turn-off disable time, t disable v dd = 3.3v, v input = 3v, r l = 15k , c l = 50pf, time into all-off state, time is highly dependent on the load (r l , c l ) time constant. 25 - 120 - ns skew, (t skewout - t skewin ) v dd = 3.3v, sel = 0v or 3.3v, oe/alm = v dd , r l = 45 , c l = 10pf, t r = t f = 500ps at 480mbps, (duty cycle = 50%) (see figure 6) 25 - 50 - ps rise/fall degradation (propagation delay), t pd v dd = 3.3v, sel = 0v or 3.3v, oe/alm = v dd , r l = 45 , c l = 10pf ( see figure 6) 25 - 250 - ps crosstalk v dd = 3.3v, r l = 50 , f = 240mhz (see figure 5) 25 - -32 - db off-isolation v dd = 3.3v, r l = 50 , f = 240mhz 25 - -30 - db -3db bandwidth signal = 0dbm, 0.2vdc offset, r l = 50 25 - 780 - mhz off capacitance, c hsxoff f = 1mhz, v dd = 3.3v, sel = 0v or 3.3v, oe/alm = 0v (see figure 4) 25 - 2.5 - pf com on capacitance, c dx(on) f = 1mhz, v dd = 3.3v, sel = 0v or 3.3v, oe/alm = v dd (see figure 4) 25 - 5.4 - pf electrical specifications - 2.7v to 5.25v supply test conditions: v dd = +3.3v, gnd = 0v, v sel h = 1.4v, v sel l = 0.5v, v oe/almh =1.4v, v oe/alml = 0.5v, (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units isl54224
6 fn6969.0 june 7, 2010 com on capacitance, c dx(on) f = 240mhz, v dd = 3.3v, sel = 0v or 3.3v, oe/alm = v dd (see figure 4) 25 - 3.3 - pf power supply characteristics power supply range, v dd full 2.7 5.25 v positive supply current, i dd v dd = 5.25v, sel = 0v or v dd , oe/alm = v dd 25 - 45 58 a full - - 66 a positive supply current, i dd v dd = 3.6v, sel = 0v or v dd , oe/alm = v dd 25 - 23 30 a full - - 35 a positive supply current, i dd v dd = 3.6v, sel = 0v or v dd , oe/alm = 0v 25 - 23 30 a full - - 35 a positive supply current, i dd v dd = 4.3v, sel = 2.6v, oe/alm = 0v or 2.6v 25 - 35 45 a full - - 52 a positive supply current, i dd v dd = 3.6v, sel = 1.4v, oe/alm = 0v or 1.4v 25 - 25 32 a full - - 38 a digital input characteristics input voltage low, v sell , v oe/alml v dd = 2.7v to 3.6v full - - 0.5 v input voltage high, v selh , v oe/almh v dd = 2.7v to 3.6v full 1.4 - 5.25 v input voltage low, v sell , v oe/alml v dd = 3.7v to 4.2v full - - 0.7 v input voltage high, v selh , v oe/almh v dd = 3.7v to 4.2 full 1.7 --v input voltage low, v sell , v oe/alml v dd = 4.3v to 5.25v full - - 0.8 v input voltage high, v selh , v oe/almh v dd = 4.3v to 5.25v full 2.0 --v input current, i sell , i oe/alml v dd = 5.25v, sel = 0v, oe/alm = 0v full - 2 - na input current, i selh v dd = 5.25v, sel = 5.25v, 4m pull-down resistor full - 1.4 - a input current, i oe/almh v dd = 5.25v, oe/alm = 5.25v, 4m pull-down resistor full - 1.4 - a notes: 10. v logic = input voltage to perform proper function. 11. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and ar e not production tested 13. flatness is defined as the di fference between maximum and minimum value of on-resistance over the specified analog signal range 14. r on matching between channels is calculated by subtracting the channel with the highest max r on value from the channel with lowest max r on value, between hsd2+ and hsd2- or between hsd1+ and hsd1-. 15. limits established by characterization and are not production tested. electrical specifications - 2.7v to 5.25v supply test conditions: v dd = +3.3v, gnd = 0v, v sel h = 1.4v, v sel l = 0.5v, v oe/almh =1.4v, v oe/alml = 0.5v, (note 10), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 11, 12) typ max (notes 11, 12) units isl54224
7 fn6969.0 june 7, 2010 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points repeat test for all switches. c l includes fixt ure and stray capacitance. figure 2b. test circuit figure 2. break-before-make time figure 3. r on test circuit 50% t r < 20ns t f < 20ns t off 90% vdd 0v v input 0v t on logic input switch input switch output 90% v out v out v (input) r l r l r on + ----------------------- - = switch input vin v out r l c l dx hsdxx sel gnd v dd c oe/alm v input 90% vdd 0v t d logic input switch output 0v v out vin sel dx r l c l v out 10pf 50 hsd2x v dd gnd v input c oe/alm hsd1x v dd c ov or vdd hsdx dx sel gnd v hsdx v 1 r on = v 1 /17ma 17ma repeat test for all switches. oe/alm isl54224
8 fn6969.0 june 7, 2010 figure 4. capacitance test circuit figure 5. crosstalk test circuit figure 6a. measurement points figure 6b. test circuit figure 6. skew test test circuits and waveforms (continued) vdd c gnd hsdxx dx sel impedance analyzer 0v or repeat test for all switches. oe/alm vdd analyzer vdd c hsd1x signal generator r l gnd sel dx 50 nc dx hsd2x signal direction through switch is reversed. repeat test for all switches. oe/alm vin din+ din- out+ out- 50% 50% 90% 10% 10% 10% 10% 90% 90% 50% 90% 50% t ri t fi t ro t f0 t skew_i t skew_o out+ c l comd1 d2 gnd vdd c d1 comd2 c l out- din+ din- |tro - tri| delay due to switch for rising input and rising output signals. |tfo - tfi| delay due to switch for fa lling input and falling output signals. |tskew_0| change in skew through the switch for output signals. |tskew_i| change in skew through the switch for input signals. 15.8 15.8 143 143 45 45 sel vin oe/alm isl54224
9 fn6969.0 june 7, 2010 application block diagram detailed description the isl54224 device is a dual single pole/double throw (spdt) analog switch configured as a dpdt that operates from a single dc power supply in the range of 2.7v to 5.25v. it was designed to function as a dual 2-to-1 multiplexer to select between two usb high-speed differential data signals in portable battery powered products. it is offered in a tdfn, and a small tqfn packages for use in mp3 players, cameras, pdas, cellphones, and other personal media players. the part contains special overvoltage detection and protection (ovp) circuitry on the d-/d+ com pins. this circuitry acts to open the usb in-line switches when the part senses a voltage on the com pins that is >3.8v (typ) or < -0.5v (typ). it isolates voltages up to 5.25v and down to -5v from getting through to the other side of the switch to protect the usb transceivers connected at the signal pins (hsd1-, hsd1+, hsd2-, hsd2+). the device has an open drain oe/alm pin that can be driven ?low? to open all switches. the oe/alm pin gets internally pulled ?low? whenever the part senses an overvoltage condition. the pin must be externally pulled ?high? with a 100k pull-up resistor and monitored for a ?low? to determine when an overvoltage condition has occurred. the part consists of four 6.5 high speed (hsx) switches. these switches have high bandwidth and low capacitance to pass usb high-speed (480mbps) differential data signals with minimal edge and phase distortion. they can also swing from 0v to 3. 6v to pass usb full speed (12mbps) differential data signals with minimal distortion. the isl54224 was designed for mp3 players, cameras, cellphones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these usb sources to a single usb host (computer). a typical application block diagram of this functionality is previously shown. a detailed description of the hs switches is provided in the following section. high-speed (hsx) data switches the hsx switches (hsd1-, hsd1+, hsd2-, hsd2+) are bi-directional switches that can pass usb high-speed and usb full-speed signals when v dd is in the range of 2.7v to 5.25v. when powered with a 2.7v supply, these switches have a nominal r on of 6.5 over the signal range of 0v to 400mv with a r on flatness of 0.3 . the r on matching between the hsd1x switches and hsd2x switches over this signal range is only 0.2 , ensuring minimal impact by the switches to usb high-s peed signal transitions. as the signal level increases, the r on switch resistance increases. at a signal level of 3.3v, the switch resistance is nominally 12 . see figures 9, 10, 11, 12, 13, 14, 15, and 16 in the ?typical performance curves? beginning on page 12. the hsx switches were specifically designed to pass usb 2.0 high-speed (480mbps) differential signals in the range of 0v to 400mv. they have low capacitance and high bandwidth to pass the usb high-speed signals with minimum edge and phase distortion to meet usb 2.0 high speed signal quality specifications. see figure 20 in the ?typical performance curves? on page 14 for usb high-speed eye pattern taken with switch in the signal path. portable media device isl54224 usb transceiver high-speed usb connector d- d+ sel gnd hsd1- hsd1+ hsd2- hsd2+ vdd oe/alm logic circuitry controller usb transceiver full-speed vbus d- d+ gnd or full-speed high_speed or ovp #1 #2 4m 4m 100k 500 3.3v 3.3v isl54224
10 fn6969.0 june 7, 2010 the hsx switches can also pass usb full-speed signals (12mbps) with minimal distor tion and meet all the usb requirements for usb 2.0 full-speed signaling. see figure 21 in the ?typical performance curves? on page 14 for usb full-speed eye pattern taken with switch in the signal path. the hs1 channel switches are active (turned on) whenever the sel voltage is logic ?0?(low) and the oe/alm voltage is logic ?1?(high). the hs2 channel switches are active (turned on) whenever the sel voltage is logic ?1? (high) and the oe/alm voltage is logic ?1? (high). overvoltage protection (ovp) the maximum normal operating signal range for the hsx switches is from 0v to 3.6v. for normal operation, the signal voltage should not be allowed to exceed this voltage range or go below ground by more than -0.3v. however, in the event that a positive voltage > 3.8v (typ) to 5.25v, such as the usb 5v v bus voltage, gets shorted to one or both of the com+ and com- pins or a negative voltage < -0.5v (typ) to -5v gets shorted to one or both of the com pins, the isl54224 has ovp circuitry to detect the overvoltage condition and open the spdt switches to prevent damage to the usb down-stream transceivers connected at the signal pins (hs1d-, hs1d+, hs2d-, hs2d+). the ovp and power-off protection circuitry allows the com pins (d-, d+) to be driven up to 5.25v while the v dd supply voltage is in the range of 0v to 5.25v. in this condition the part draws < 100a of i comx and i dd current and causes no stress to the ic. in addition, the spdt switches are off and the fault voltage is isolated from the other side of the switch. the oe/alm pin gets interna lly pulled low whenever the part senses an overvoltage condition. the pin must be externally pulled ?high? with a pull-up resistor and monitored for a ?low? to dete rmine when an overvoltage condition has occurred. external v dd series resistor to limit i dd current during nega tive ovp condition a 100 to 1k resistor in series with the vdd pin (see figure 7) is required to limit the i dd current draw from the system power supply rail during a negative ovp fault event. with a negative -5v fault voltage at both com pins, the graph in figure 8 shows the idd current draw for different external resistor values for supply voltages of 2.7v, 3.6v, and 5.25v. note: with a 500 resistor the current draw is limited to around 5ma. when the negative fault voltage is removed the i dd current will return to it?s normal operation current of 25 a to 45 a. the series resistor also provides improved esd and latch-up immunity. during an overvoltage transient event (such as occurs during system level iec 61000 esd testing), substrate currents can be generated in the ic that can trigger parasitic scr structures to turn on, creating a low impedance path from the vdd power supply to ground. this will result in a significant amount of current flow in the ic, which can potentially create a latch-up state or permanently damage the ic. the external vdd resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. under normal operation, the low microamp i dd current of the ic produces an insignificant voltage drop across the series resistor resulting in no impact to switch operation or performance . isl54224 operation the following will discuss using the isl54224 shown in the ?application block diagram? on page 9. power the power supply connected at the vdd pin provides the dc bias voltage required by the isl54224 part for proper operation. the isl54224 can be operated with a v dd voltage in the range of 2.7v to 5.25v. figure 7. v dd series resistor to limit idd current during negative ovp and for enhanced esd and latch-up immunity figure 8. negative ovp idd current vs resistor value vs v supply sel d+ d- gnd ovp logic vdd oe/alm hsd1+ 100 to 1k v supply c protection resistor hsd1- i dd -5v fault voltage pulled ?low? to indicate ovp hsd2+ hsd2- 100k v supply 0 5 10 15 20 25 100 200 300 400 500 600 700 800 900 1k resistor ( ) i dd (ma) v com+ = v com- = -5v 2.7v 3.6v 5.25v isl54224
11 fn6969.0 june 7, 2010 for lowest power consumption you should use the lowest v dd supply. a 0.01f or 0.1f decoupling capacitor should be connected from the vdd pin to ground to filter out any power supply noise from entering the part. the capacitor should be located as close to the vdd pin as possible. in a typical application, v dd will be in the range of 2.8v to 4.3v and will be connected to the battery or ldo of the portable media device. logic control the state of the isl54224 device is determined by the voltage at the sel pin and the oe/alm pin. sel is only active when the oe/alm pin is logic ?1? (high). refer to ?truth table? on page 2. the isl54224 logic pins are designed to minimize current consumption when the logic control voltage is lower than the v dd supply voltage. with v dd = 3.6v and logic pins at 1.4v the part typically draws only 25a. with v dd = 4.3v and logic pins at 2.6v the part typically draws only 35a. driving the logic pins to the v dd supply rail minimizes power consumption. the sel pin and oe/alm pin have special circuitry that allows them to be driven with a voltage higher than the v dd supply voltage. these pins can be driven up to 5.25v with a v dd supply in the range of 2.7v to 5.25v. the sel pin and oe/alm pin are internally pulled low through 4m resistors to ground and can be tri-stated by a processor. the oe/alm pin is an open dr ain connection. it should be pulled high through an external 100k pull-up resistor. the oe/alm pin can then be driven ?low? by a processor to open all switches or it can be monitored by the processor for a ?low? when the part goes into an over-voltage condition. logic control voltage levels hsd1 usb channel if the sel pin = logic ?0? and the oe/alm pin = logic ?1?, high-speed channel 1 will be on. the hsd1- and hsd1+ switches are on and the hsd2- and hsd2+ switches are off (high impedance). when a computer or usb hub is plugged into the common usb connector and channel 1 is active, a link will be established between the usb 1 transceiver section of the media player and the computer. the device will be able to transmit and receive data from the computer. hsd2 usb channel if the sel pin = logic ?1? and the oe/alm pin = logic ?1?, high-speed channel 2 will be on. the hsd2- and hsd2+ switches are on and the hsd1- and hsd1+ switches are off (high impedance). when a usb cable from a computer or usb hub is connected at the common usb connector and channel 2 is active, a link will be established between the usb 2 driver section of the media player and the computer. the device will be able to transmit and receive data from the computer. all switches off mode if the sel pin = logic ?0? or logic ?1? and the oe/alm pin = logic ?0?, all of the switches will turn off (high impedance). the all off state can be used to switch between the two usb sections of the media player. when disconnecting from one usb device to the other usb device, you can momentarily put the isl54224 switch in the ?all off? state in order to get the computer to disconnect from the one device so it can pr operly connect to the other usb device when that channel is turned on. whenever the isl54224 senses a fault condition on the com pins, the oe/alm pin will be internal pulled low by the device and all switches will be turned off. usb 2.0 v bus short requirements the usb specification in section 7.1.1 states a usb device must be able to withstand a v bus short (4.4v to 5.25v) or a -1v short to the d+ or d- signal lines when the device is either powered off or powered on for at least 24 hours. the isl54224 part has special power-off protection and ovp detection circuitry to meet these short circuit requirements. this circuitry allows the isl54224 to provide protection to the usb down-stream transceivers connected at its signal pi ns (hs1d-, hs1d+, hs2d-, hs2d+) to meet the usb specification short circuit requirements. the power-off protection and ovp circuitry allows the com pins (d-, d+) to be driven up to 5.25v or down to -5v while the v dd supply voltage is in the range of 0v to 5.25v. in these overvoltage conditions with a 500 external vdd resistor the part draws < 55 a of current into the com pins and causes no stress/damage to the ic. in addition, all switches are off and the shorted v bus voltage will be isolated from getting through to the other side of the switch channels, thereby protecting the usb transceivers. table 2. logic control voltage levels v dd supply range logic = ?0? (low) logic = ?1? (high) oe/alm sel oe/alm sel 2.7v to 3.6v 0.5v or floating 0.5v or floating 1.4v 1.4v 3.7v to 4.2v 0.7v or floating 0.7v or floating 1.7v 1.7v 4.3v to 5.25v 0.8v or floating 0.8v or floating 2.0v 2.0v isl54224
12 fn6969.0 june 7, 2010 typical performance curves t a = +25c, unless ot herwise specified figure 9. on-resistance vs supply voltage vs switch voltage figure 10. on-resistance vs supply voltage vs switch voltage figure 11. on-resistance vs supply voltage vs switch voltage figure 12. on-resistance vs switch voltage figure 13. on-resistance vs switch voltage figure 14. on-resistance vs switch voltage 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) i com = 17ma 2.7v 3.0v 3.3v 3.6v 4.3v 5.25v 0 5 10 15 20 25 30 0 0.6 1.2 1.8 2.4 3.0 3.6 r on ( ) v com (v) 3.3v i com = 17ma 2.7v 3.0v 4 6 8 10 12 0 0.6 1.2 1.8 2.4 3.0 3.6 r on ( ) v com (v) i com = 17ma 4.3v 3.6v 5.25v 4 5 6 7 8 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) +25c +85c -40c i com = 17ma v dd = 2.7v 4 5 6 7 8 00.10.20.30.4 r on ( ) v com (v) +25c +85c -40c i com = 17ma v dd = 3.3v 4 5 6 7 8 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) +25c +85c -40c i com = 17ma vdd = 4.3v isl54224
13 fn6969.0 june 7, 2010 figure 15. on-resistance vs switch voltage figure 16. on-resistance vs switch voltage figure 17. digital switching point vs supply voltage figure 18. oe/alm iol vs vol during ovp state figure 19. oe/alm leakage current vs di gital voltage during normal operation typical performance curves t a = +25c, unless ot herwise specified (continued) 0 5 10 15 20 25 30 0 0.6 1.2 1.8 2.4 3.0 3.6 r on ( ) v com (v) i com = 17ma +25c +85c -40c v dd = 2.7v 0 3 6 9 12 15 18 0 0.6 1.2 1.8 2.4 3.0 3.6 r on ( ) v com (v) +25c +85c -40c i com = 17ma v dd = 3.3v 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.7 3.2 3.7 4.2 4.7 5.25 v dd (v) v inh and v inl (v) v inh v inl -40c to +85c v ol/alm voltage (v) i ol/alm current (ma) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4 3 2 1 05.25 v dd = 2.7v v dd = 5.25v d+ = d- = 5v (ovp) 0 2 4 6 8 10 12 012345 v ol/alm voltage (v) v dd = 2.7v d+ = d- = 3v (normal operation) i ol/alm leakage current (a) v dd = 5.25v isl54224
14 fn6969.0 june 7, 2010 figure 20. eye pattern: 480mbps with usb switches in the signal path figure 21. eye pattern: 12mbps with usb switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) voltage scale (0.1v/div) v dd = 3.3v time scale (0.2ns/div) time scale (10ns/div) voltage scale (0.5v/div) v dd = 3.3v isl54224
15 fn6969.0 june 7, 2010 figure 22. frequency response figure 23. off-isolation figure 24. crosstalk die characteristics substrate and tdfn thermal pad potential (powered up): gnd transistor count: 1297 process: submicron cmos typical performance curves t a = +25c, unless ot herwise specified (continued) -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 1m 10m 100m 1g v in = 0dbm, 0.86vdc bias r l = 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001 0.01 0.1 1m 10m 100 500 frequency (mhz) normalized gain (db) v in = 0dbm, 0.2vdc bias r l = 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 frequency (mhz) normalized gain (db) v in = 0dbm, 0.2vdc bias r l = 50 0.001 0.01 0.1 1 10 100 500 isl54224
16 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6969.0 june 7, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl54224 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 6/7/10 fn6969.0 initial release. isl54224
17 fn6969.0 june 7, 2010 isl54224 package outline drawing l10.1.8x1.4a 10 lead ultra thin quad flat no-lead plastic package rev 5, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 jedec reference mo-255. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 0.08 seating plane 0.10 c c c see detail "x" max. 0.55 0 .1 27 ref 0-0.05 c 2x 0.10 1.40 1.80 b a 6 7 1 5 6x 0.40 c c 4 0.10 m ma b 0.70 pin #1 id 2 10 index area pin 1 0.50 10x 0.20 6 6 4x 0.30 0.05 1 3 8 9 x 0.40 6 7 1 5 (6x 0.40) (0.70) 10 (0.70) (10x 0.20) (4x 0.30) 3 8 (9 x 0.60) package outline
18 fn6969.0 june 7, 2010 isl54224 thin dual flat no-lead plastic package (tdfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k l1 9 l m l10.3x3a 10 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 2.95 3.0 3.05 - d2 2.25 2.30 2.35 7, 8 e 2.95 3.0 3.05 - e2 1.45 1.50 1.55 7, 8 e 0.50 bsc - k 0.25 - - - l 0.25 0.30 0.35 8 n 10 2 nd 5 3 rev. 4 8/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for d2 dimensions. ( 2.90 ) (1.50) ( 10x 0.25) ( 10x 0.50) ( 2.30 ) ( 2.00 ) typical recommended land pattern (8x 0.50) pin 1

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